Publications

2025

1. CAM

   Configurable DSP-Based CAM Architecture for Data-Intensive Application FPGAs

   Design Automation Conference (DAC), 2025

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   Content-addressable memory (CAM) is a type of fast memory unique in its ability to perform parallel searches of stored data based on content rather than specific memory addresses. They have been used in many domains, such as networking, databases, and graph processing. Field-programmable gate arrays (FPGAs) are an attractive means to implement CAMs because of their low latency, reconfigurable, and energy-efficient nature. However, such implementations also face significant challenges, including high resource utilization, limited scalability, and suboptimal performance due to the extensive use of look-up tables (LUTs) and block RAMs (BRAMs). These issues stem from the inherent limitations of FPGA architectures when handling the parallel operations required by CAMs, often leading to inefficient designs that cannot meet the demands of high-speed, data-intensive applications. To address these challenges, we propose a novel configurable CAM architecture that leverages the digital signal processing (DSP) blocks available in modern FPGAs as the core resource. By utilizing DSP blocks’ data storage and logic capabilities, our approach enables configurable CAM architecture with efficient multi-query support while significantly reducing search and update latency for data-intensive applications. The DSP-based CAM architecture offers enhanced scalability, higher operating frequencies, and improved performance compared to traditional LUT and BRAM-based designs. In addition, we demonstrate the effectiveness of our proposed CAM architecture with a triangle counting application on real graphs. This innovative use of DSP blocks also opens up new possibilities for high-performance, data-intensive applications on FPGAs. Our proposed design is open-sourced at: https://github.com/ddiwu/CAM/

2024

1. SerDes

   A 4x6.25-Gbs Serial Link Transmitter Core in 0.18-μm CMOS for high-speed front-end ASICs

   Real Time, 2024

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   In this paper, a 4x6.25 Gbps serial link transmitter core has been designed for high-speed front-end ASICs. The transmitter core is implemented in a commercial 0.18 um CMOS technology. The core consists of a common PLL and four individual transmitter channels. Each channel contains a 2-stage 20:2 serializer, a 2-stage half-rate feed-forward equalizer and a clock manager circuit. A new architecture of the clock and data path is proposed, and the overall power consumption is reduced by 40% compared with previous works. At a data rate of 6.25 Gbps, the simulation results show that the PLL and transmitter feature a phase jitter of 1.3 ps RMS and 11.2 ps pk-pk respectively. The 4-channel transmitter core occupies 0.44 mm2 and dissipates 27.7 mW/Gbps from 1.8 V supply. The chip is being packaged and will be tested soon in December.

2. Chem

   Thiol Ligand-Modified Au for Highly Efficient Electroreduction of Nitrate to Ammoniar

   Precious Chemistry, 2024

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   Electroreduction of nitrate (NO3-) to ammonia (NH3) is an environmentally friendly route for NH3 production, serving as an appealing alternative to the Haber–Bosch process. Recently, various noble metal-based electrocatalysts have been reported for electroreduction of NO3–. However, the application of pure metal electrocatalysts is still limited by unsatisfactory performance, owing to the weak adsorption of nitrogen-containing intermediates on the surface of pure metal electrocatalysts. In this work, we report thiol ligand-modified Au nanoparticles as the effective electrocatalysts toward electroreduction of NO3–. Specifically, three mercaptobenzoic acid (MBA) isomers, thiosalicylic acid (ortho-MBA), 3-mercaptobenzoic acid (meta-MBA), and 4-mercaptobenzoic acid (para-MBA), were employed to modify the surface of the Au nanocatalyst. During the NO3– electroreduction, para-MBA modified Au (denoted as para-Au/C) displayed the highest catalytic activity among these Au-based catalysts. At −1.0 V versus reversible hydrogen electrode (vs RHE), para-Au/C exhibited a partial current density for NH3 of 472.2 mA cm–2, which was 1.7 times that of the pristine Au catalyst. Meanwhile, the Faradaic efficiency (FE) for NH3 reached 98.7% at −1.0 V vs RHE for para-Au/C. The modification of para-MBA significantly improved the intrinsic activity of the Au/C catalyst, thus accelerating the kinetics of NO3– reduction and giving rise to a high NH3 yield rate of para-Au/C.